Wireless receivers, such as the ones provided in mobile telephones, generally comprise an analog to digital converter (ADC) that converts the received signal into a digital signal that can be processed by a digital signal processor or the like. The analog to digital conversion is often performed using a discrete-time technique according to which the received signal is sampled at a sampling frequency fs, and then the samples are processed using an ADC such as a ΣΔ ADC. In order to reduce the operating frequency of the ADC, decimation may be applied to the analog samples before applying the digital conversion.
FIG. 1A is a graph illustrating an example of such an analog to digital conversion based on an input analog voltage signal 102. The signal 102 initially has a generally sinusoidal form, and then its amplitude drops to a low level close to zero. As represented by dots 104 in FIG. 1A, the signal 102 is sampled at time intervals ts, where ts=1/fs, fs being the sampling frequency. The voltage level of each sample is then for example converted into a digital value by selecting a closest level of quantization, each level of quantization having a corresponding digital value. The sampling continues even when the input signal falls close to zero, and thus the power consumed by the ADC remains at a constant level. Thus a drawback of performing such discrete-time analog to digital conversion is that it is has relatively high power consumption when the wireless transmission is sparse in the time domain. A further drawback of this type of analog to digital conversion is that sampling the signal at the sampling frequency fs risks bringing out-of-band interferers into the signal band, and thus an antialiasing filter is generally required to remove such interferers before sampling.
To address these drawbacks, a continuous-time analog to digital conversion method has been proposed. For example, such a method is described in the publication by B. Schell et al. entitled “A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation”, IEEE Journal of Solid-State Circuits, Vol. 43, No. 11, November 2008, the contents of which is hereby incorporated by reference.
FIG. 1B is a graph illustrating an example of continuous-time analog to digital conversion, based on the same input voltage signal 102 as in FIG. 1A. As illustrated, an output continuous-time digital signal is generated, which for example has one of a limited number of levels, there being seven levels illustrated by horizontal dashed lines in the example of FIG. 1B. A threshold voltage is for example defined at the mid-point between each pair of adjacent levels, and each time the input signal passes one of the threshold voltages, the level of the output signal switches levels accordingly.
It can be seen that when the input signal falls to zero, threshold voltages are no longer crossed by the input signal, and thus the output signal remains at a constant level, leading to very low power consumption. Furthermore, because the input signal is not sampled at a fixed time interval, aliasing is no longer an issue, and thus an anti-aliasing filter is not required.
The analog to digital conversion technique represented by FIG. 1B is referred to herein as a “continuous-time” technique because the input signal is not sampled at fixed time intervals, but rather the input signal is continually monitored. Furthermore, this conversion technique is asynchronous, because the output signal may switch from one level to another at any time based on the level of the input signal.
While such a continuous-time ADC consumes low power while the input signal is sparse in the time domain, the consumption can be high when high activity signals such as sinusoids are present. This is a configuration very often encountered by radio back-ends where the useful signal can be corrupted by high power interferers. There is thus a need in the art for an analog to digital converter having low power consumption even in the presence of such interferers.